Development Systems

It’s very easy to start developing for CHERIoT with either an Arty A7 or lowRISC Sonata FPGA board, or with no hardware  using a simulator. 

The Sonata boards (which, unlike the A7, are designed specifically for prototyping CHERIoT-based systems) are now available to buy from Mouser which is a significant improvement for availability and shipment globally.

For those unfamiliar with the platform the CHERIoT Getting Started Guide on https://cheriot.org explains how to build and run code for allof the board support packages an simulator.

As easy as Pi...

Many organizations are worried about the transition to the RISC-V architecture, or the introduction of CHERI technology into their projects. Please don't worry... we have evolved a From zero to CHERIoT in two minutes with Sonata blog post hat explains how to start building and running code on Sonata in about the same amount of time as it will take you to get the board out of its box and plug it in.

Similary people worry about the impact of CHERI on their code base. In recent examples SCI ported the FreeRTOS Network Stack from traditional Arm implementation to RISC-V. The effort was minimal and primarily focused on enhancing the code orientation to make it more reusable in a compartmentalised form, definitely a "nice to have" rather than strictly required. The total impact on the code was <0.2% of the code was changed, a minimal impact that moved the stack from a single flat code space implementation, to a full compartmentalise and ruggidised solution that resolved 100% of the known CVEs.

RT*M

For those who wish to understand more before jumping into GitHub and starting to code, there is an exceptional online resource, the CHERIoT Programmers' Guide.
The guid outlines the C/C++ extensios for CHERIot, communications between threads and advice on writing device drivers, amongst other key considerations.